1. Field of the Invention
The present invention relates to the phase synchronization of one or more digital units to a low frequency reference pulse train, and more particularly to such an arrangement in which each digital unit contains a digital divider chain (or .div. N counter) the sequence of which is to be synchronized to a predetermined phase of the reference pulse.
2. Description of the Prior Art
One known prior art approach for synchronizing one or more digital units to a common low frequency reference is the provision of a central timing unit with a plurality of cable paths for transmitting all synchronization signals from the central unit to each digital unit requiring synchronization. For example, in the field of time base synchronization of video equipment, such as the synchronization of a number of television cameras, the synchronization signals including a horizontal drive, vertical drive, mixed blank signal and mixed sync signal would be fed from the central unit to each camera by four cable circuits. A shortcoming of this approach is that it requires bulky coaxial transmission lines and is particularly cumbersome where substantial cable lengths are required.
Another known approach is to establish a source of a low frequency synchronization pulse train, and then to provide individual digital divider chains within the digital units which are to be brought into common synchronization. Each divider chain is driven by a phase lock loop synchronized to the source of reference pulses. Typically, the phase lock loop employs a voltage controlled multi-vibrator, some type of phase detector and an integrating network (having a low pass filter). The phase detector detects the phase error between the incoming signal and the output of the voltage controlled multi-vibrator. This error signal is integrated and applied to the voltage controlled oscillator for control thereof to establish the desired synchronization. This approach is of particular utility in conjunction with the time base generated video equipment, since each unit frequently contains its own divider chain. However, this approach exhibits shortcomings due to the lack of stability and the temperature dependence of any digital to analog control situation. Further, the low pass filter and voltage controlled multi-vibrator each require large capacitor RC networks, which is a drawback when MHP or LSI forms of high density packing fabrication are required.
Still another known prior art approach employs the phase lock loop concept of detection of an error signal which alters the count periods. The divider chain includes circuit elements which basically alter the counter construction, typically in the form of addition/subtraction of a single bit in the counter chain. This system phase shifts the divider chain either ahead or backward in time in increments associated with the addition/subtraction logic. A shortcoming of this approach is inherent lack of stability, particularly in television camera synchronization where the vertical interval switching among the units should be positively stable in order to avoid presentation break-up when transferring from one video source to another. Also, the requirement of a specialized counter circuit structure is a drawback when MHP of LSI forms of fabrication are desired, since tailor-made counters for such constructions are very expensive.
Yet another approach is disclosed in U.S. Pat. No. 3,755,748, entitled "Digital Phase Shifter/Synchronizer And Method of Shifting" to E. Carlow and E. Hepworth. Like the previous two approaches, a single cable circuit transmits the low frequence reference from the common source to the individual units, and each individual unit contains a divider chain. The pulse train driving the divider chain is incrementally shifted either forward or backward by one-half cycle increments responsive to a phase comparison to the reference pulse train. Like the approach of the addition/subtraction logic built into the count chain, this approach has the shortcoming of less than desired stability for maintenance of precise vertical interval lock with television camera units. Also, the approach requires at least five flip-flops and eight logic elements and therefore is a relatively complex circuit, with commensurate higher costs of MHP and LSI fabrication.